High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory. In recent years, there has been an effort to further increase the speed of memory access.
In conventional peripheral circuitries for a semiconductor memory device, for example, pads and data input/output circuits are arranged in a corresponding manner across layers. For example, a semiconductor memory device may include a data input/output circuit. To achieve high speed transmission, the impedance of the data input/output circuit should be controlled. To control the impedance, an external resistance, such as ZQ resistor may be coupled. The semiconductor memory device including a plurality of chips are generally provided with one external ZQ resistor. When two or more chips request to use the ZQ resistor at the same time, an arbiter circuit is typically used to determine which chip should access the ZQ resistor. Accordingly, one chip can access the ZQ resistor, and a subsequent chip may access the ZQ resistor after ZQ calibration for the one chip has been completed.
For example, arbiter circuits may rely on a voltage based arbitration scheme to determine which chip, a master chip or slave chip, has issued a ZQ calibration request. In the voltage based arbitration scheme, a ZQ calibration request issued by the master chip may have a strong pulldown, while a ZQ calibration request issued by the slave chip may have a weak pulldown. Thus, various states of use of the ZQ resistor may be determined, via a ZQ pad voltage. However, chip packages with multiple-chips and/or of a low-power consumption type may not be able to effectively differentiate between multiple states via the ZQ pad voltage by the voltage based arbitration scheme.
For example, some recent semiconductor devices (e.g., low-power double data rate synchronous DRAM), such as Low Power Double Data Rate 4 (LPDDR4), adopted a time based arbitration scheme. Under the time based arbitration scheme, each chip sharing a ZQ resistor is programmed with a unique time delay to create a master-slave hierarchy. This time based arbitration scheme enables any number of chips in the semiconductor memory device per package to use the ZQ resistor, although the required time increases exponentially according to the number of chips. For example, the semiconductor memory device including 16 chips sharing a single ZQ resistor may need 16 different delay variations for the 16 chips.
Thus, an arbitration circuit implementing an arbitration scheme is needed for a semiconductor memory device having a larger number of chips to complete the ZQ calibration without extending time for ZQ calibration request arbitration.